Test Rig Design
Table Of Content
Test Rig Definition
Test Rig represents a one click automation to build, deploy and test a software module. Successful execution of test rig would ascertain complete setup of the MOSIP platform.
Test-Rig comprises of multiple components starting from:
Kubernetes env setup
Pulling the source code from the GIT repository
Running sonarqube tests for static code analysis
Building the application using maven
Automated application deployment using Kubernetes
Running automated unit tests
Running automated tests to verify and validate the application build against the given requirements.
Test Automation [↑]
MOSIP platform architecture is mainly based on Micro services and SEDA architecture. Therefore it predominantly comprises of Rest & JAVA APIs. Therefore test automation best serves the purpose of detailed API level testing. Test automation is the key to the successful testing of individual APIs and their interrelation with interdependent APIs. It ensures comprehensive test coverage and test data.
Automation deliverables mainly comprises of individual module level suites for the individual MOSIP modules:
Pre-Registration
Registration Client
Registration Processor
IDA
Kernel
Additionally there will be an end to end, system level test suite that will cut across all modules covering the functionality
Module Level Automation Suites [↑]
The below diagram depicts the various building blocks of the module level suite.
Salient features
The automation suite is configurable to selectively execute tests such as Sanity or/and Regression
Each module level suite covers API and inter API automation
The individual module level test suites and the end to end suite are triggered via the CI/CD pipeline and run post application deployment
The user guides listed below detail the usage of individual module level automation suites
System Level or E2E Automation Suite (Test Rig) [↑]
End to end system level Test Rig covers the functionality across the modules starting with Pre-Registration and ending in Registration Processor or IDA.
The below diagram depicts the overall design of the end to end suite.
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